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| DATA SHEET MOS INTEGRATED CIRCUIT PD17225, 17226, 17227, 17228 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER DESCRIPTION PD17225, 17226, 17227, 17228 (hereafter called PD17225 subseries) are 4-bit single-chip microcontrollers for small general-purpose infrared remote control transmitters. It employs a 17K architecture of general-purpose register type devices for the CPU, and can directly execute operations between memories instead of the conventional method of executing operations through the accumulator. Moreover, all the instructions are 16-bit 1-word instructions which can be programmed efficiently. In addition, a one-time PROM model, PD17P218, to which data can be written only once, is also available. It is convenient either for evaluating the PD17225 subseries programs or small-scale production of application systems. Detailed functions are described in the following manual. Be sure to read this manual when designing your system. PD172xx Subseries User's Manual: U12795E FEATURES * Infrared remote controller carrier generator circuit (REM output) * 17K architecture: General-purpose register system * Program memory (ROM), Data memory (RAM) PD17225 Program memory (ROM) 4 K bytes (2048 x 16) Data memory (RAM) PD17226 8 K bytes (4096 x 16) PD17227 12 K bytes (6144 x 16) PD17228 16 K bytes (8192 x 16) 111 x 4 bits 223 x 4 bits * 8-bit timer : 1 channel * Basic internal timer/Watchdog timer : 1 channel (WDOUT output) * Instruction execution time (can be changed in two steps) at fX = 4 MHz at fX = 8 MHz * External interrupt pin (INT) * I/O pins * Supply voltage : 4 s (high-speed mode)/8 s (ordinary mode) : 2 s (high-speed mode)/4 s (ordinary mode) :1 : 20 : VDD = 2.2 to 3.6 V (at fX = 8 MHz (high-speed mode)) VDD = 2.0 to 3.6 V (at fX = 4 MHz (high-speed mode)) * Low-voltage detector circuit (mask option) Unless otherwise specified, the PD17225 is treated as the representative model throughout this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12643EJ2V0DS00 (2nd edition) Date Published April 1999 N CP (K) Printed in Japan The mark shows major revised points. (c) 1997,1999 PD17225, 17226, 17227, 17228 APPLICATION Preset remote controllers, toys, portable systems, etc. ORDERING INFORMATION Part Number Package 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 30-pin plastic shrink SOP (300 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 30-pin plastic shrink SOP (300 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 30-pin plastic shrink SOP (300 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 30-pin plastic shrink SOP (300 mil) PD17225CT-xxx PD17225GT-xxx PD17225MC-xxx-5A4 PD17226CT-xxx PD17226GT-xxx PD17226MC-xxx-5A4 PD17227CT-xxx PD17227GT-xxx PD17227MC-xxx-5A4 PD17228CT-xxx PD17228GT-xxx PD17228MC-xxx-5A4 Remark xxx indicates ROM code suffix. DIFFERENCE BETWEEN PD17225 SUBSERIES AND PD17215 SUBSERIES Item Supply Voltage Instruction Execution Time (tCY) PD17225 Subseries VDD = 2.0 to 3.6 V 2 s (VDD = 2.2 to 3.6 V) 4 s (VDD = 2.0 to 3.6 V) Connected to RESET pin or VDD via resistor (when not used) PD17215 Subseries VDD = 2.0 to 5.5 V 2 s (VDD = 3.5 to 5.5 V) 4 s (VDD = 2.2 to 5.5 V) 8 s (VDD = 2.0 to 5.5 V) Connected to RESET pin or GND (when not used) WDOUT Pin Connection of WDOUT pin differs between PD17P218 and PD17225, 17226, 17227, and 17228 when OTP is evaluated on PD17225 subseries board and when WDOUT pin is not used. When PD17P218 is used, malfunctioning does not occur even when WDOUT pin is pulled up, though connection can be changed by using a jumper switch on the external board. Others Supply voltage, low-voltage detection voltage, oscillator characteristics, and noise characteristics differ. Although PD17P218 is used as one-time PROM for evaluation for both subseries, PD17P218 cannot be used to evaluate the low-voltage high-speed operation of the PD17225 subseries. 2 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 PIN CONFIGURATION (TOP VIEW) * 28-pin plastic SOP (375 mil) PD17225GT-xxx, 17226GT-xxx, 17227GT-xxx, 17228GT-xxx * 28-pin plastic shrink DIP (400 mil) PD17225CT-xxx, 17226CT-xxx, 17227CT-xxx, 17228CT-xxx P0D 2 P0D 3 INT P0E 0 P0E 1 P0E 2 P0E 3 REM V DD X OUT X IN GND RESET WDOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P0D 1 P0D 0 P0C 3 P0C 2 P0C 1 P0C 0 P0B 3 P0B 2 P0B 1 P0B 0 P0A 3 P0A 2 P0A 1 P0A 0 Data Sheet U12643EJ2V0DS00 3 PD17225, 17226, 17227, 17228 * 30-pin plastic shrink SOP (300 mil) PD17225MC-xxx-5A4, PD17226MC-xxx-5A4, PD17227MC-xxx-5A4, PD17228MC-xxx-5A4 P0D2 P0D3 INT P0E0 P0E1 P0E2 P0E3 REM VDD XOUT XIN GND RESET WDOUT IC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IC2 P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0 GND IC1, IC2 INT : Ground : Internally connected : External interrupt request signal input P0A0-P0A3 : Input port (CMOS input) P0B0-P0B3 : Input port (CMOS input) P0C0-P0C3 : Output port (N-ch open-drain output) P0D0-P0D3 : Output port (N-ch open-drain output) P0E0-P0E3 : I/O port (CMOS push-pull output) REM RESET VDD WDOUT XIN, XOUT : Remote controller output (CMOS push-pull output) : Reset input : Power supply : Hang-up/low voltage detection output (N-ch open-drain output) : Resonator connection 4 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 BLOCK DIAGRAM P0A0 P0A1 P0A2 P0A3 RAM PD17225, 17226 : 111 x 4 bits PD17227, 17228 : 223 x 4 bits P0A RF Remote Control Divider REM 8-bit Timer P0B0 P0B1 P0B2 P0B3 P0B SYSTEM REG. Interrupt Controller ALU INT P0C0 P0C1 P0C2 P0C3 P0C ROM PD17225 : 2048 PD17226 : 4096 PD17227 : 6144 PD17228 : 8192 x x x x 16 bits 16 bits 16 bits 16 bits Instruction Decoder P0D0 P0D1 P0D2 P0D3 P0D RESET WDOUT Program Counter P0E0 P0E1 P0E2 P0E3 P0E Stack (5 levels) Power Supply Circuit CPU Clock VDD GND Basic Interval/ Watchdog Timer XIN OSC XOUT Data Sheet U12643EJ2V0DS00 5 PD17225, 17226, 17227, 17228 CONTENTS 1. PIN FUNCTIONS ........................................................................................................................... 1.1 1.2 1.3 Pin Function List ................................................................................................................................ Input/Output Circuits ......................................................................................................................... Processing of Unused Pins .............................................................................................................. 8 8 9 10 2. MEMORY SPACE ......................................................................................................................... 2.1 2.2 2.3 2.4 2.5 Program Counter (PC) ....................................................................................................................... Program Memory (ROM) ................................................................................................................... Stack ................................................................................................................................................... Data Memory (RAM) ........................................................................................................................... Register File (RF) ............................................................................................................................... 11 11 11 13 15 22 3. PORTS ........................................................................................................................................... 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Port 0A (P0A0-P0A3) ........................................................................................................................... Port 0B (P0B0-P0B3) ........................................................................................................................... Port 0C (P0C0-P0C3) ........................................................................................................................... Port 0D (P0D0-P0D3) ........................................................................................................................... Port 0E (P0E0-P0E3) ........................................................................................................................... INT Pin ................................................................................................................................................. Switching Bit I/O ................................................................................................................................ Specifying Pull-up Resistor Connection ......................................................................................... 25 25 25 25 25 25 26 27 28 4. CLOCK GENERATOR CIRCUIT .................................................................................................. 4.1 Instruction Execution Time (CPU Clock) Selection ........................................................................ 29 29 5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT ..................... 5.1 5.2 5.3 Configuration of 8-bit Timer (with modulo function) ..................................................................... Function of 8-bit Timer (with modulo function) .............................................................................. Carrier Generator Circuit for Remote Controller ............................................................................ 30 30 32 33 6. BASIC INTERVAL TIMER/WATCHDOG TIMER .......................................................................... 6.1 6.2 6.3 Source Clock for Basic Interval Timer ............................................................................................. Controlling Basic Interval Timer ...................................................................................................... Operation Timing for Watchdog Timer ............................................................................................ 37 37 37 39 7. INTERRUPT FUNCTIONS ............................................................................................................ 7.1 7.2 7.3 Interrupt Sources ............................................................................................................................... Hardware of Interrupt Control Circuit .............................................................................................. Interrupt Sequence ............................................................................................................................ 40 40 41 44 6 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 8. STANDBY FUNCTIONS ................................................................................................................ 8.1 8.2 8.3 8.4 8.5 HALT Mode ......................................................................................................................................... HALT Instruction Execution Conditions .......................................................................................... STOP Mode ......................................................................................................................................... STOP Instruction Execution Conditions ......................................................................................... Releasing Standby Mode .................................................................................................................. 46 46 47 48 49 49 9. RESET ........................................................................................................................................... 9.1 9.2 9.3 Reset by Reset Signal Input ............................................................................................................. Reset by Watchdog Timer (Connect RESET and WDOUT pins) ................................................... Reset by Stack Pointer (Connect RESET and WDOUT pins) ........................................................ 50 50 50 51 10. LOW-VOLTAGE DETECTOR CIRCUIT (CONNECT RESET AND WDOUT PINS) .................... 52 11. ASSEMBLER RESERVED WORDS ............................................................................................. 11.1 11.2 Mask Option Directives ..................................................................................................................... Reserved Symbols ............................................................................................................................. 53 53 54 12. INSTRUCTION SET ...................................................................................................................... 12.1 12.2 12.3 12.4 Instruction Set Outline ...................................................................................................................... Legend ................................................................................................................................................ List of Instruction Sets ...................................................................................................................... Assembler (RA17K) Built-In Macro Instruction .............................................................................. 60 60 61 62 64 13. ELECTRICAL SPECIFICATIONS ................................................................................................. 65 14. APPLICATION CIRCUIT EXAMPLE ............................................................................................ 71 15. PACKAGE DRAWINGS ................................................................................................................ 72 16. RECOMMENDED SOLDERING CONDITIONS ............................................................................ APPENDIX A. DIFFERENCES AMONG PD17225, 17226, 17227, 17228 AND PD17P218 ......... APPENDIX B. FUNCTIONAL COMPARISON OF PD17225 SUBSERIES RELATED PRODUCTS .. 75 76 78 APPENDIX C. DEVELOPMENT TOOLS ............................................................................................ 80 Data Sheet U12643EJ2V0DS00 7 PD17225, 17226, 17227, 17228 1. 1.1 PIN FUNCTIONS Pin Function List Symbol P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 P0C1 P0C2 P0C3 P0D0 P0D1 P0D2 P0D3 P0E0 P0E1 P0E2 P0E3 Function 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. When at least one of these pins goes low, standby function is released. Output Form On Reset Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 4 5 6 7 (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (1) (2) (4) (5) (6) (7) - Input 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. When at least one of these pins goes low, standby function is released. - Input 4-bit N-ch open-drain output port. Can be used for key source output of key matrix. N-ch open-drain Low-level output 4-bit N-ch open-drain output port. Can be used for key source output of key matrix. N-ch open-drain Low-level output 4-bit input/output port. Can be set in inputset in input or output mode in 1-bit units. In output mode, this port functions as a high current CMOS output port. In input mode, function as CMOS input and can be specified to connect pull-up resistor by program. Outputs transfer signal for infrared remote controller. Active-high output. System reset input. CPU can be reset when low-level signal is input to this pin. While low-level signal is input, oscillator is stopped. Can be connected to pull-up resistor by mask option. Power supply Ground External interrupt request signal input Output detecting hang-up and drop in supply voltage. This pin outputs at low level either when an overflow occurs in the watchdog timer, when an overflow/underflow occurs in the stack, or when the supply voltage drops below a specified level (mask option). Connect this pin to the RESET pin. Connects ceramic resonator for system clock oscillation These pins cannot be used. Leave open. CMOS push-pull Input 8 (8) REM CMOS push-pull Low-level output 13 (13) RESET - Input 9 (9) 12 (12) 3 (3) VDD GND INT - - - - - Input Highimpedance Low-level output at low voltage detection (Oscillation stops) - 14 (14) WDOUT N-ch open-drain 11 (11) 10 (10) (15) (30) XIN XOUT IC1 IC2 - - Remark The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP. 8 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 1.2 Input/Output Circuits The equivalent input/output circuit for each PD17225 pin is shown below. (1) P0A, P0B (4) RESET VDD V DD (Mask option) Input buffer (2) P0C, P0D Input buffer Schmitt trigger input with hysteresis data Output latch N-ch characteristics (5) INT (3) P0E VDD Input buffer data Pull-up register VDD data Output latch P-ch P-ch Schmitt trigger input with hysteresis characteristics output disable N-ch (6) REM VDD Selector Input buffer data P-ch output disable N-ch (7) WDOUT data N-ch Data Sheet U12643EJ2V0DS00 9 PD17225, 17226, 17227, 17228 1.3 Processing of Unused Pins Process the unused pins as follows: Table 1-1. Processing of Unused Pins Pin P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 Connect to VDD. Connect to VDD. Connect to GND. Connect to GND. Input : Individually connect to VDD or GND via resistor. Output : Leave open. Leave open. Connect to GND. Connect to VDD via resistor. These pins cannot be used. Leave open. Recommended Connection REM INT WDOUT IC1, IC2 10 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 2. 2.1 MEMORY SPACE Program Counter (PC) The program counter (PC) specifies an address of the program memory (ROM). The program counter is an 11/12/13-bit binary counter as shown in Figure 2-1. Its contents are initialized to address 0000H at reset. Figure 2-1. Configuration of Program Counter Page MSB PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 LSB PC0 PC (PD17225) PC (PD17226) PC (PD17227, 17228) 2.2 Program Memory (ROM) The configuration of the program memory is as follows: Part Number Capacity 2048 x 16 bits 4096 x 16 bits 6144 x 16 bits 8192 x 16 bits Address 0000H-07FFH 0000H-0FFFH 0000H-17FFH 0000H-1FFFH PD17225 PD17226 PD17227 PD17228 The program memory stores a program, interrupt vector table, and fixed data table. The program memory is addressed by the program counter. Figure 2-2 shows the program memory map. The entire range of the program memory can be addressed by the BD addr, BR @AR, CALL @AR, MOVT DBF, and @AR instructions. Note, however, that the subroutine entry addresses that can be specified by the CALL addr instruction are from 0000H to 07FFH. Data Sheet U12643EJ2V0DS00 11 PD17225, 17226, 17227, 17228 Figure 2-2. Program Memory Map Address 0000H 0001H 0002H 0003H 16 bits Reset start address Basic interval timer interrupt vector External input (INT) interrupt vector 8-bit timer interrupt vector ( PD17225) Subroutine entry Page 0 addresses for CALL addr instruction Branch addresses for BR addr instruction Branch addresses for BR @AR instruction 07FFH 0FFFH ( PD17226) Page 1 Subroutine entry addresses for CALL @AR instruction 17FFH ( PD17227) ( PD17228) Page 2 Page 3 Table reference addresses for MOVT DBR, @AR instruction 1FFFH 12 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 2.3 Stack A stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 2.3.1 Stack configuration Figure 2-3 shows the stack configurarion. A stack consists of a stack pointer (a 4-bit binary counter, the high-order 1 bit fixed to 0), five 11-bit (PD17225)/12bit (PD17226)/13-bit (PD17227, 17228) address stack registers, and three 5-bit (PD17225, 17226)/6-bit (PD17227, 17228) interrupt stack registers. Figure 2-3. Stack Configuration Stack pointer (SP) b3 0 b2 b1 b0 0H 1H 2H 3H 4H 5H WDOUT pin goes low when the contents of the stack pinter are 6H-7H. 6H 7H b12 b11 b10 b9 b8 Address stack registers (ASR) b7 b6 b5 b4 b3 b2 b1 b0 SPb2 SPb1 SPb0 Address stack register 0 Address stack register 1 Address stack register 2 Address stack register 3 Address stack register 4 Undefined Undefined Undefined PD17225 PD17226 PD17227, 17228 Interrupt stack registers (INTSK) b5 0H BANKSK0 1H 2H BANKSK1 BANKSK2 b4 BCDSK0 BCDSK1 BCDSK2 b3 CMPSK0 CMPSK1 CMPSK2 b2 CYSK0 CYSK1 CYSK2 b1 ZSK0 ZSK1 ZSK2 b0 IXESK0 IXESK1 IXESK2 PD17225, 17226 PD17227, 17228 Data Sheet U12643EJ2V0DS00 13 PD17225, 17226, 17227, 17228 2.3.2 Function of stack The address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. It also stores the contents of the address registers (ARs) when a stack manipulation instruction (PUSH AR) is executed. The WDOUT pin goes low if a subroutine call or interrupt exceeding 5 levels is executed. The interrupt stack register (INTSK) saves the contents of the bank register (BANK) and program status word (PSWORD) when an interrupt is accepted. The saved contents are restored when an interrupt return (RETI) instruction is executed. INTSK saves data each time an interrupt is accepted, but the data stored first is lost if more than 3 levels of interrupts occur. 2.3.3 Stack Pointer (SP) and Interrupt Stack Pointer Table 2-1 shows the operations of the stack pointer (SP). The stack pointer can take eight values, 0H-07. Because there are only five stack registers available, however, the WDOUT pin goes low if the value of SP is 6 or greater. Table 2-1. Operations of Stack Pointer Instruction CALL addr CALL @AR MOVT DBF, @AR (1st Instruction Cycle) PUSH AR When Interrupt Is Accepted RET RETSK MOVT DBF, @AR (2nd Instruction Cycle) POP AR RETI +1 +1 +1 0 -1 -1 -1 0 Value of Stack Pointer (SP) Counter of Interrupt Stack Register 14 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 2.4 Data Memory (RAM) Data memory (random access memory) stores data for operations and control. It can be read-/write-accessed by instructions. 2.4.1 Memory configuration Figure 2-4 shows the configuration of the data memory (RAM). The data memory consists of two "banks": BANK0 and BANK1. In each bank, every 4 bits of data is assigned an address. The high-order 3 bits of the address indicate a "row address" and the low-order 4 bits of the address indicate a "column address". For example, a data memory location indicated by row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores data of 4 bits (= a "nibble"). In addition, the data memory is divided into following six functional blocks: (1) System register (SYSREG) A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles long) of each bank. In other nibbles, each bank has a system register at its addresses 74H to 7FH. (2) Data buffer (DBF) A data buffer is resident on addresses 0CH to 0FH (4 nibbles long) of bank 0 of data memory. The reset value is 0320H. (3) General register (GR) A general register is resident on any row (16 nibbles long) of any bank of data memory. The row address of the general register is pointed by the general pointer (RP) in the system register (SYSREG). (4) Port register A port data register is resident on addresses 6FH, and 70H to 73H (5 nibbles) of BANK0 of data memory. No data can be written to the addresses 70H to 73H of BANK1 (the values of addresses 70H to 73H of BANK0 are read in this case). PD17225 and 17226 are not provided with BANK1. Data Sheet U12643EJ2V0DS00 15 PD17225, 17226, 17227, 17228 (5) General-purpose data memory The general-purpose data memory area is an area of the data memory excluding the system register area, and the port register area. This memory area has a total of 223 nibbles (111 nibbles in BANK0 and 112 nibbles in BANK1). PD17225 and 17226 are not provided with BANK1. Figure 2-4. Configuration of Data Memory Column address 0 0 Row address BANK 0 6 7 8 9 A B C D E F 1 2 3 4 5 Data buffer (DBF) 1 2 3 4 5 6 7 P0A P0B P0C P0D System register (SYSREG) P0E Example Address 1AH in BANK 0 0 1 Column address 2 3 4 5 6 BANK 1 7 8 9 A B C D E F Row address System register (SYSREG) Caution No data can be written to the addresses 70H to 73H of BANK1 (the value of P0A to P0D are read in this case). 16 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 2.4.2 System registers (SYSREG) The system registers are registers that are directly related to control of the CPU. These registers are mapped to addresses 74H-7FH on the data memory and can be referenced regardless of bank specification. The system registers include the following registers: * Address registers (AR0-AR3)Note * Window register (WR) * Bank register (BANK) Note * Memory pointer enable flag (MPE) * Memory pointers (MPH, MPL) * Index registers (IXH, IXM, IXL) * General register pointers (RPH, RPL) * Program status word (PSWORD) Note The address register (AR3) and the bank register (BANK) are fixed to 0 in the PD17225 and 17226. Figure 2-5. Configuration of System Register Address 74H 75H 76H 77H 78H 79H 7AH 7BH Index register (IX) 7CH 7DH General register pointer (RP) 7EH 7FH Program status word (PSWORD) Name Address register (AR) Window Bank register register (WR) (BANK) Data memory row address pointer (MP) IXH MPH IXM MPL IXL Symbol Bit AR 3 AR 2 AR 1 AR 0 WR BANK RPH RPL PSW b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 (WR) (AR) ( PD17227, 17228) (AR) ( PD17226) (AR) ( PD17225) (IX) 000 * (RP) Data 000 0000 (BANK) M 000 P000* *E (MP) * I BCC CMY Z X E DP 00000 Initial Value At Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note *: This bit is fixed to 0 in the PD17225 and 17226. Data Sheet U12643EJ2V0DS00 17 PD17225, 17226, 17227, 17228 2.4.3 General register (GR) A general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) Configuration of general register Figure 2-6 shows the configuration of the general register. A general register occupies 16 nibbles (16 x 4 bits) on a selected row address of the data memory. The row address is selected by the general register pointer (RP) of the system register. The RP having four significant bits in the PD17227 and 17228 can point to any row address in the range of 0H to 7H of each bank (BANK0 and BANK1). In the PD17225 and 17226, 3 bits are available in the RP. These bits can point to any row address in the range of 0H to 7H of BANK0. (2) Functions of the general register The general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. As a general register is a part of the data memory, you can say that the general register enables arithmetic operation and data transfer between two locations of the data memory. Similarly, the general register can be accessed by a data memory manipulation instruction as it is a part of the data memory. Figure 2-6. Configuration of General Registers General register pointer (RP) RPH RPL 0 1 A s s i g n e d t o 2 3 4 5 6 7 Port register BANK1 System registers RP Port register BANK0 0 1 2 3 4 5 6 Column address 7 8 9 A B C D E F b 3 b 2 b 1 b 0 b3 b2 b1 b 0 F i x e d t o 0 F i x e d t o 0 F i x e d t o 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 General registers (16 nibbles) Example General registers when RP = 0000010B General register settable range 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 B C1 D 2 f 3 l a4 g5 6 7 System registers Same system registers exist 18 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 2.4.4 Data buffer (DBF) The data buffer on the addresses 0CH to 0FH of data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) Functions of the data buffer The data buffer has two major functions: a function to transfer to and from hardware and a function to read constant data from the program memory (for table reference). Figure 2-7 shows the relationship between the data buffer and peripheral hardware. Figure 2-7. Data Buffer and Peripheral Hardware Data buffer (DBF) Peripheral address Internal bus 05H, 06H Peripheral hardware 8-bit timer (TMC, TMM) Carrier generator for remote controller (NRZLTMM, NRZHTMM) Address register (AR) 03H, 04H 40H Program memory (ROM) Constant data Data Sheet U12643EJ2V0DS00 19 PD17225, 17226, 17227, 17228 Table 2-2. Relations between Hardware Peripherals and Data Buffer Hardware Peripherals Name Peripheral Register Transferring Data with Data Buffer Symbol Peripheral Address 05H 06H Data Buffer Used DBF0, DBF1 DBF0, DBF1 PUT/GET 8-Bit Timer 8-bit counter 8-bit modulo register TMC TMM GET only PUT only Remote Controller Carrier Generator NRZ low-level timer modulo register NRZ high-level timer modulo register NRZLTMM 03H DBF0, DBF1 PUT GET NRZHTMM 04H DBF0, DBF1 PUT (clear bit 3 of DBF1 to 0) GET (bits 3 of DBF1 is always 0) PUT (bits 0-3 of AR3 and bit 3 of AR2 are any)Note 1 GET (bits 0-3 of AR3 and bit 3 of AR2 are always 0)Note 2 Address Register Address register AR 40H DBF0-DBF3 Notes 1. In the PD17226: bits 0 to 3 of AR3 are any, in the PD17227, 17228: bits 1 to 3 of AR3 are any 2. In the PD17226: bits 0 to 3 of AR3 are always 0, in the PD17227, 17228: bits 1 to 3 of AR3 are always 0 (2) Table reference A MOVT instruction reads constant data from a specified location of the program memory (ROM) and sets it in the data buffer. The function of the MOVT instruction is explained below. MOVT DBF, @AR: Reads data from a program memory location pointed to by the address register (AR) and sets it in the data buffer (DBF). Data buffer DBF 3 DBF 2 DBF 1 DBF 0 Program memory (ROM) MOVT DBF, @ AR 16 bits b15 b0 20 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 (3) Note on using data buffer When transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing PUT), and read-only peripheral registers (only when executing GET) must be handled as follows: * When device operates Nothing changes even if data is written to the read-only register. If the unused address is read, an undefined value is read. Nothing changes even if data is written to that address. * Using assembler An error occurs if an instruction is executed to read a write-only register. Again, an error occurs if an instruction is executed to write data to a read-only register. An error also occurs if an instruction is executed to read or write an unused address. * If an in-circuit emulator (IE-17K or IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. Nothing changes even if data is written to a read-only register, and an error does not occur. An undefined value is read if an unused address is read; nothing changes even if data is written to this address. An error does not occur. Data Sheet U12643EJ2V0DS00 21 PD17225, 17226, 17227, 17228 2.5 Register File (RF) The register file mainly consists of registers that set the conditions of the peripheral hardware. These registers can be controlled by dedicated instructions PEEK and POKE, and the embedded macro instructions of RA17K, SETn, CLRn, and INITFLG. 2.5.1 Configuration of register file Figure 2-8 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE instructions. The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers are assigned to addresses 00H-3FH regardless of the bank, the addresses 00H-3FH of the general-purpose data memory cannot be accessed when the PEEK or POKE instruction is used. The addresses that can be accessed by the PEEK and POKE instructions are the addresses 00H-3FH of the control registers and 40H-7FH of the general-purpose data memory. The register file consists of these addresses. The control registers are assigned to addresses 80H-BFH on the IE-17K to facilitate debugging. Figure 2-8. Register File Access with PEEK or POKE Instructions 0 0 1 2 3 4 5 6 7 1 2 3 4 5 Column address 6 7 8 9 A B C D E F Data memory POKE M063, WR Row address System register 0 1 2 POKE LCDMD, WR 3 Register file Control register PEEK WR, SP 22 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 2.5.2 Control registers The control registers consists of a total of 64 nibbles (64 x 4 bits) of the addresses 00H-3FH of the register file. Of these, however, only 14 nibbles are actually used. The remaining 50 nibbles are unused registers that are inhibited from being read or written. When the "PEEK WR, rf" instruction is executed, the contents of the register file addressed by "rf" are read to the window register. When the "POKE rf, WR" instruction is executed, the contents of the window register are written to the register file addressed by "rf". When using the assembler (RA17K), the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. The macro instructions allow the contents of the register file to be manipulated in bit units. For the configuration of the control register, refer to Figure 11-1 Register File List. SETn CLRn SKTn SKFn NOTn INITFLG : Sets flag to "1" : Sets flag to "0" : Skips if all flags are "1" : Skips if all flags are "0" : Complements flag : Initializes flag INITFLGX : Initalizes flag 2.5.3 Notes on using register files When using the register files, bear in mind the points described below. For details, refer to PD172xx subseries User's Manual (U12795E). (1) When manipulating control registers (read-only and unused registers) When manipulating the write-only (W), the read-only (R) and unused control registers by using the assembler or in-circuit emulator, keep in mind the following points: * When device operates Nothing changes even if data is written to the read-only register. If the unused register is read, an undefined value is read; nothing is changed even if data is written to this register. * Using assembler An error occurs if instruction is excecuted to read data to the write-only register. An error occurs if an instruction is executed to write data to the read-only register. An error also occurs if an instruction is executed to read or write the unused address. * When an in-circuit emulator (IE-17K or IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if the write-only register is read, and an error does not occur. Nothing changes even if data is written to the read-only register, and an error does not occur. An undefined value is read if the unused address is read; nothing changes even if data is written to this address. An error does not occur. Data Sheet U12643EJ2V0DS00 23 PD17225, 17226, 17227, 17228 (2) Symbol definition of register file An error occurs if a register file address is directly specified as a numeral by the operand "rf" of the "PEEK WR, rf" or "POKE rf, WR" instruction if the 17K Series Assembler (RA17K) is being used. Therefore, the addresses of the register file must be defined in advance as symbols. To define the addresses of the control registers as symbols, define them as the addresses 80H-BFH of BANK0. The portion of the register file overlapping the data memory (40H-7FH), however, can be defined as symbols as is. 24 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 3. 3.1 PORTS Port 0A (P0A0-P0A3) This is a 4-bit input port. Data is read through port register P0A (address 70H). This port is a CMOS input port with a pull-up resistor, and can be used for key return input for a key matrix. When a low-level signal is input to at least one of the pins in this port in the standby mode, the standby mode is released. 3.2 Port 0B (P0B0-P0B3) This is a 4-bit input port. Data is read through port register P0B (address 71H). This port is a CMOS input port with a pull-up resistor, and can be used for key return input for a key matrix. When a low-level signal is input to at least one of the pins in this port in the standby mode, the standby mode is released. 3.3 Port 0C (P0C0-P0C3) This is a 4-bit output port. The contents of the output latch are read and output data is set through port register P0C (address 72H). This port is an N-ch open-drain output port, and can be used as the key source of a key matrix. In the standby mode, this port outputs low-level signals. 3.4 Port 0D (P0D0-P0D3) This is a 4-bit output port. The contents of the output latch are read and output data is set through port register P0D (address 73H). This port is an N-ch open-drain output port, and can be used as the key source for a key matrix. In the standby mode, this port outputs low-level signals. 3.5 Port 0E (P0E0-P0E3) This is a 4-bit I/O port which can be set in either the input or output mode in 1-bit units by the P0EBIO (address 27H) of the register file. To read the input data or to set the output data, use the P0E register (address 6F). When data is read in the output mode, the contents of the output latch are read. Connection of a pull-up resistor can be specified in 1-bit units by the P0EBPU (address 17H) of the register file. (When the pull-up resistor is connected, note that the pull-up resistor is not disconnected even when the output mode is set.) On reset, this port functions as an input port. Data Sheet U12643EJ2V0DS00 25 PD17225, 17226, 17227, 17228 3.6 INT Pin This pin inputs an external interrupt request signal. At either the rising or falling edge of the signal input to this pin, the IRQ flag (RF: address 3EH, bit 0) is set. The status of this pin can be read by using the INT flag (RF: address 0FH, bit 0). When the high level is input to the pin, the INT flag is set to "1"; when the low level is input, the flag is reset to "0" (refer to 7.2.1 INT). Figure 3-1. Relations between Port Register and Each Pin Contents to Be Read Bank Address Port Bit b3 P0A3 b2 P0A2 70H Port 0A b1 P0A1 b0 P0A0 Input only b3 P0B3 b2 P0B2 71H Port 0B b1 P0B1 b0 P0B0 b3 P0C3 b2 P0C2 0 72H Port 0C b1 P0C1 b0 P0C0 b3 P0D 3 b2 P0D 2 73H Port 0D b1 P0D 1 b0 P0D 0 b3 P0E3 b2 P0E2 6FH Port 0E b1 P0E1 b0 P0E0 COMS push-pull Pin status N-ch open-drain (Output only) - Output latch Pin status - Output Form Input Mode Contents to Be Written Output Mode On Reset Output Mode Input Mode - - Input mode (w/pull-up resistor) - Output latch Output mode (Low level output) Output latch Input mode (w/pull-up resistor) 26 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 3.7 Switching Bit I/O The I/O which can be set in the input or output mode in bit units is called a bit I/O. P0E is a bit I/O port, which can be set in the input or output mode in bit units by the register file shown below. When the mode is changed from input to output, the P0E output latch contents are output to the port lines, as soon as the mode has been changed. 3 P0EBIO3 2 P0EBIO2 1 P0EBIO1 0 P0EBIO0 Address: RF : 27H On reset: 0H R/W: R/W P0EBIO0 0 1 Sets P0E0 Input/Output Mode Sets P0E0 in input mode Sets P0E0 in output mode P0EBIO1 0 1 Sets P0E1 Input/Output Mode Sets P0E1 in input mode Sets P0E1 in output mode P0EBIO2 0 1 Sets P0E2 Input/Output Mode Sets P0E2 in input mode Sets P0E2 in output mode P0EBIO3 0 1 Sets P0E3 Input/Output Mode Sets P0E3 in input mode Sets P0E3 in output mode Data Sheet U12643EJ2V0DS00 27 PD17225, 17226, 17227, 17228 3.8 Specifying Pull-up Resistor Connection Whether or not a pull-up resistor is connected to port P0E can be specified by the following registers of the register file in 1-bit units when the port is in the input modeNote. 3 2 1 0 Address: RF : 17H On reset: 0H R/W: R/W P0EBPU3 P0EBPU2 P0EBPU1 P0EBPU0 P0EBPU0 Connects Pull-Up Resistor to P0E0 0 1 Not connected Connected P0EBPU1 Connects Pull-Up Resistor to P0E1 0 1 Not connected Connected P0EBPU2 Connects Pull-Up Resistor to P0E2 0 1 Not connected Connected P0EBPU3 Connects Pull-Up Resistor to P0E3 0 1 Not connected Connected Note To disconnect the pull-up resistor in the output mode, clear the corresponding bit of the P0EBPU register. 28 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 4. 4.1 CLOCK GENERATOR CIRCUIT Instruction Execution Time (CPU Clock) Selection The PD17225 is equipped with a clock oscillator that supplies clocks to the CPU and hardware peripherals. Instruction execution time can be changed in two steps (ordinary mode and high-speed mode) without changing the oscillation frequency. To change the instruction execution time, change the mode of SYSCK (RF: address 02H) of the register file by using the POKE instruction. Note, that the mode is actually only changed when the instruction next to the POKE instruction has been executed. When using the high-speed mode, pay attention to the supply voltage. (Refer to 13. ELECTRICAL SPECIFICATIONS.) At reset, the ordinary mode is set. 3 0 2 0 1 0 0 SYSCK Address: RF : 02H On reset: 0H R/W: R/W SYSCK 0 1 Selects Instruction Execution Time Ordinary mode 32/fX (8 s) High-speed mode 16/fX (4 s) Figures in ( ): indicate figures when system clock fX = 4 MHz. Data Sheet U12643EJ2V0DS00 29 PD17225, 17226, 17227, 17228 5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT The PD17225 is equipped with the 8-bit timer which is mainly used to generate the leader pulse of the remote controller signal, and to output codes. 5.1 Configuration of 8-bit Timer (with modulo function) Figure 5-1 shows the configuration of the 8-bit timer. As shown in this figure, the 8-bit timer consists of an 8-bit counter (TMC), an 8-bit modulo register (TMM), a comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the operation clock of the 8-bit timer. To start/stop the 8-bit timer, and to reset the 8-bit counter, TMEN (address 33H, bit 3) and TMRES (address 33H, bit 2) of the register file are used. To select the operation clock of the 8-bit timer, use TMCK1 (address 33H, bit 1) and TMCK0 (address 33H, bit 0) of the register file. The value of the 8-bit counter is read by using the GET instruction through DBF (data buffer). No value can be set to the 8-bit counter. A value is set to the modulo register by using the PUT instruction through DBF. The value of the modulo register cannot be read. When the value of the counter coincides with that of the modulo register, an interrupt flag (IRQTM: address 3FH, bit 0) of the register file is set. TMC 7 6 5 4 3 2 1 0 Address Peripheral register: 05H On reset 00H R/W R 8-bit counter TMM 7 6 5 4 3 2 1 0 Address Peripheral register: 06H On reset FFH R/W W 8-bit modulo register Caution Do not clear TMM to 0 (IRQTM is not set). 30 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 Figure 5-1. Configuration of 8-bit Timer and Remote Controller Carrier Generator Circuit Data buffer Internal bus 8-bit timer RF : 33H TMEN TMRES TMCK1 TMCK0 fX/32 fX/64 fX/256 Selector 8-bit modulo register TMM Comparator IRQTM R S Q 8-bit counter TMC Remote controller carrier generator circuit fX/2 SW 7-bit counter RF : 11H Comparator bit 7 x 7-bit modulo register NRZLTMM NRZ NRZBF RF : 12H 7-bit counter Comparator bit 7 0 fixed 7-bit modulo register NRZHTMM REM Remark TMM, TMC, NRZLTMM, and NRZHTMM are peripheral registers. Data Sheet U12643EJ2V0DS00 31 PD17225, 17226, 17227, 17228 5.2 Function of 8-bit Timer (with modulo function) 3 TMEN 2 TMRES 1 TMCK1 0 TMCK0 Address RF : 33H On reset 8H Note 1 R/W R/W Note 2 TMCK1 0 0 1 1 TMCK0 0 1 0 1 8-Bit Timer Clock Source Selection Count clock: fX/32 (Measurement time range: 8 s to 2.048 ms) Count clock: fX/64 (Measurement time range: 16 s to 4.096 ms) Count clock : fX/256 (Measurement time range: 64 s to 16.384 ms) Remote control carrier generation circuit output Value indicated by parentheses is for when ( ): f SYS (system clock) = fX = 4MHz TMRES 0 1 8-Bit Timer Reset Flag Data read out is always "0" Resets 8-bit counter and IRQTM TMEN 0 1 8-Bit Timer Count Enable Flag Stops 8-bit timer count operation Enable 8-bit timer count operation (falling edge) Notes 1. When the STOP mode is released, bit 3 must be set. 2. Bit 2 is a write-only bit. NRZLTMM 7 x 6 5 4 3 2 1 0 Address Peripheral register: 03H On reset Undefined R/W R/W 7-bit modulo register Bit 7 0 1 Output Control of REM Pin When NRZ = 1, carrier output to REM pin When NRZ = 1, high-level output to REM pin NRZHTMM 7 0 6 5 4 3 2 1 0 Address Peripheral register: 04H On reset Undefined R/W R/W 7-bit modulo register Bit 7 Fixed to 0 32 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 5.3 Carrier Generator Circuit for Remote Controller PD17225 is provided with a carrier generator circuit for the remote controller. The remote controller carrier generator circuit consists of a 7-bit counter, NRZ high-level timer modulo register (NRZHTMM), and NRZ low-level timer modulo register (NRZLTMM). The high-level and low-level periods are set in the corresponding modulo registers through the DBF to determine the carrier duty factor and carrier frequency. The system clock (fX) is divided by two and is input to the 7-bit counter. Therefore, when a 4-MHz resonator is used, 2 MHz (0.5 s) is input to the counter as the clock; when a 32-kHz oscillator (fXT) is used, 16 kHz is input. The NRZ high-level output timer modulo register is called NRZHTMM, and the NRZ low-level timer modulo register is called NRZLTMM. Data is written to these registers by the PUT instruction. The contents for these register are read by the GET instruction. Bit 7 of NRZLTMM specifies whether the carrier or high level is output to the REM pin. To output the carrier, be sure to clear bit 7 to 0. 5.3.1 Remote controller signal output control The REM pin, which outputs the carrier, is controlled by bits NRZ and NRZBF for the register file and timer 0. While the NRZ content is "1", the clock generated by the remote controller carrier generator circuit is output to the REM pin; while the NRZ content is "0", the REM pin outputs a low level. The NRZBF content is automatically transferred to NRZ by the interrupt signal generated by timer 0. If data is set in NRZBF in advance, the REM pin status changes in synchronization with the timer 0 counting operation. If the interrupt signal is generated from timer 0 with the REM pin at the high level, NRZ being "1", and the carrier clock at the high level, the REM pin output is not in accordance with the updated content of NRZ, until the carrier clock goes low. This processing is useful for holding the high level pulse width from the output carrier constant (refer to the figure below). When the content of NRZ is "0", the remote controller carrier generator circuit stops. However, if the clock for timer 0 is output from the remote controller carrier generator circuit, the clock continues to operate, even when the NRZ content becomes "0". An actual example showing a remote controller signal output to the REM pin is presented below. Data Sheet U12643EJ2V0DS00 33 PD17225, 17226, 17227, 17228 When bit 7 of NRZLTMM is 0 (carrier output) NRZ REM MAX. 500 ns (delay)Note (fX = 4 MHz) REM pin does not go low until carrier goes low even if NRZ becomes 0 Note Value when (TMCK1, TMCK0) (1, 1). When (TMCK1, TMCK0) = (1, 1), the value differs depending on how NRZ is manipulated. If NRZ is set by an instruction, the width of the first high-level pulse may be shortened. If NRZ is set by data transferred from NRZBF, the high-level pulse is delayed by the low-level pulse of the carrier clock. When bit 7 of NRZLTMM is 0 (carrier not output) NRZ REM 3 0 2 0 1 0 0 NRZ Address RF : 12H On reset 0H R/W R/W NRZ 0 1 NRZ Data Outputs low level to REM pin Outputs a carrier to REM pin or high level output 3 0 2 0 1 0 0 NRZBF Address RF : 11H On reset 0H R/W R/W NRZBF 0 1 NRZ Data Output Next NRZ buffer bit. Transfered to NRZ by interrupt signal for 8-bit timer. 34 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 Setting carrier frequency and duty factor Where the system clock frequency is fX and carrier frequency is fC: (division ratio) = fX/(2 x fC) is divided into m:n and is set in the modulo registers as follows: High-level period set value = { Low-level period set value = { Example x m/(m + n)} - 1 x n/(m + n)} - 1 Where fC = 38 kHz, duty factor (high-level period) = 1/3, and fX = 4 MHz, = 4 MHz/(2 x 38 kHz) = 52.6 m:n = 1:2 From the above, the value of the modulo register is: . High-level period = 17 . Low-level period . . 34 = Therefore, the carrier frequency is 37.74 kHz. Table 5-1. Carrier Frequency List (fX = 4 MHz) Set value tH (s) NRZHTMM 00H 01H 04H 09H 0FH 0FH 11H 11H 19H 3FH 7FH NRZLTMM 00H 02H 04H 09H 10H 21H 21H 22H 35H 3FH 7FH 0.5 1.0 2.5 5.0 8.0 8.0 9.0 9.0 13.0 32.0 64.0 0.5 1.5 2.5 5.0 8.0 17.0 17.0 17.5 27.0 32.0 64.0 tL (s) 1/fC (s) fC (kHz) Duty 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/2 1/2 1.0 2.5 5.0 10.0 16.5 25.0 26.0 26.5 40.0 64.0 120.0 1000 400 200 100 60.6 40.0 38.5 37.7 25.0 15.6 7.8 tH tL REM (fC) 1/fC Data Sheet U12643EJ2V0DS00 35 PD17225, 17226, 17227, 17228 5.3.2 Countermeasures against noise during transmission (carrier output) When a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 A may flow through the infrared LED. Since two batteries are usually used as the power source of the transmitter, several of equivalent resistance (r) exists in the power source as shown in Figure 5-2. This resistance increases to 10 to 20 if the supply voltage drops to 2 V. While the carrier is output from the REM pin (while the infrared LED lights), therefore, a highfrequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. To minimize the influence on the microcontroller of this high-frequency noise, take the following measures: <1> Separate the power lines of the microcontroller from the power lines of the infrared LED with the terminals of the batteries at the center. Use thick power lines and keep the wiring short. <2> Locate the resonator as close as possible to the microcontroller and shield it with GND lines (as indicated by the shaded portion in the figure below). <3> Locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. Also, use a capacitor to eliminate high-frequency noise. <4> To prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the CALL/RET instruction, while the carrier is output. <5> To improve the reliability in case of program hang-up, use the watchdog timer (connect the WDOUT and RESET pins). Figure 5-2. Example of Countermeasures against Noise 0.5 to 1 A Infrared LED REM VDD Microcomputer r + - Batteries RESET WDOUT VSS Remark In this figure, the RESET pin is connected to a pull-up resistor by mask option. 36 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 6. BASIC INTERVAL TIMER/WATCHDOG TIMER The basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal. 6.1 Source Clock for Basic Interval Timer 7 The system clock (fX) is divided, to generate the source clock for the basic interval timer. The input clock frequency for the basic interval timer is fX/2 . When the CPU is set in the STOP mode, the basic interval timer also stops. 6.2 Controlling Basic Interval Timer The basic interval timer is controlled by the bits on the register file. That is, the basic interval timer is reset by BTMRES. The frequency for the interrupt signal, output by the basic interval timer, is selected by BTMMD, and the watchdog timer is reset by WDTRES. Figure 6-1. Basic Interval Timer Configuration fX /2 18 fX /2 20 System clock fX 1/2 7 divider 1/2 11 divider 1/2 divider 1/2 divider 1/2 divider Selector B WDOUT BTMRES WDTRES BTMCK IRQBTM Data Sheet U12643EJ2V0DS00 37 PD17225, 17226, 17227, 17228 3 WDTRES 2 BTMCK 1 BTMRES 0 0 Address RF : 03H On reset 0H R/W R/WNote BTMRES 0 1 Basic Interval Timer Reset Data read out is always "0" Writing "1" resets basic interval timer BTMCK 0 1 Basic Interval Timer Mode Selection Generates interrupt signal IRQBTM every fX/220 Generates interrupt signal IRQBTM every fX/218 WDTRES 0 1 Watchdog Timer Reset Data read out is always "0" Writing "1" resets watchdog timer (fX/221 counter) Note Bits 1 and 3 are write-only bits. 38 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 6.3 Operation Timing for Watchdog Timer The basic interval timer can be used as a watchdog timer. Unless the watchdog timer is reset within a fixed timeNote, it judges that "the program has hung up", and the PD17225 is reset. It is therefore necessary to reset through programming the watchdog timer with in a fixed time. The watchdog timer can be reset by setting WDTRES to 1. Note Fixed time: approx. 340 ms (at 4 MHz) Cautions 1. The watchdog timer cannot be reset in the shaded range in Figure 6-2. Therefore, set WDTRES before both the fX/2 21 and fX/2 signals go high. 20 2. Refer to 9. RESET for the WDOUT pin function. Figure 6-2. Watchdog Timer Operation Timing fX/218 fX/219 fX/220 fX/221 INTBTM (fX/220) INTBTM (fX/218) WDOUT Watchdog timer reset signal WDOUT output goes low if WDTRES is not set WDTRES Setting WDTRES at this timing is invalid Data Sheet U12643EJ2V0DS00 39 PD17225, 17226, 17227, 17228 7. 7.1 INTERRUPT FUNCTIONS Interrupt Sources PD17225 is provided with three interrupt sources. When an interrupt has been accepted, the program execution automatically branches to a predetermined address, which is called a vector address. A vector address is assigned to each interrupt source, as shown in Table 7-1. Table 7-1. Vector Address Priority 1 2 3 8-bit timer Interrupt Source Ext/Int Internal External Internal Vector Address 0003H 0002H 0001H INT pin rising and falling edges Basic interval timer When more than one interrupt request is issued at the same time, the interrupts are accepted in sequence, starting from the one with the highest priority. Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which an interrupt is accepted is that the interrupt is enabled by the EI instruction. While the DI instruction is executed, or while an interrupt is accepted, the interrupt is disabled. To enable accepting an interrupt after the interrupt has been processed, the EI instruction must be executed before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, no interrupt can be accepted between the EI and RETI instructions. Caution In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack by the hardware, to a maximum of three levels. Also, within the interrupt processing contents, when peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents are not saved by the hardware. Accordingly, it is recommended that at the beginning of interrupt processing DBF and WR be saved by software to RAM, and immediately before finishing interrupt processing the saved contents be returned to thier original location. 40 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 7.2 Hardware of Interrupt Control Circuit This section describes the flags of the interrupt control circuit. (1) Interrupt request flag and interrupt enable flag The interrupt request flag (IRQxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is excuted. An interrupt enable flag (IPxxx) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) EI/DI instruction Whether an accepted interrupt is executed or not is specified by the EI or DI instruction. When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by an instruction. The DI flag clears the INTE flag to 0 to disable all the interrupts. The INTE flag is also cleared to 0 at reset, disabling all the interrupts. Table 7-2. Interrupt Request Flags and Interrupt Enable Flag Interrupt Request Flag IRQTM IRQ IRQBTM Signal Setting Interrupt Request Flag Reset by 8-bit timer. Set when edge of INT pin input signal is detected Reset by basic interval timer. Interrupt Enable Flag IPTM IP IPBTM 7.2.1 INT This flag reads the INT pin status. When a high level is input to the INT pin, this flag is set to "1"; when a low level is input, the flag is reset to "0". 3 0 2 0 1 0 0 INT Address RF : 0FH On reset Undefined R/W R INT 0 1 INT Pin Level Detection INT pin : Low level INT pin : High level Data Sheet U12643EJ2V0DS00 41 PD17225, 17226, 17227, 17228 7.2.2 IEG This pin selects the interrupt edge to be detected on the INT pin. When this flag is "0", the interrupt is detected at the rising edge; when it is "1", the interrupt is detected at the falling edge. 3 0 2 0 1 0 0 IEG Address RF : 1FH On reset 0H R/W R/W IEG 0 1 INT Pin Interrupt Detection Edge Selection Rising edge of INT pin Falling edge of INT pin 7.2.3 Interrupt enable flag This flag enables each interrupt source. When this flag is "1", the corresponding interrupt is enabled; when it is "0", the interrupt is disabled. 3 0 2 IPBTM 1 IP 0 IPTM Address RF : 2FH On reset 0H R/W R/W IPTM 0 1 8-Bit Timer Interrupt Enable Flag Disables interrupt acceptance by 8-bit timer Enables interrupt acceptance by 8-bit timer IP 0 1 INT Pin Interrupt Enable Flag Disables interrupt acceptance by INT pin input Enables interrupt acceptance by INT pin input IPBTM 0 1 Basic Interval Timer Interrupt Enable Flag Disables interrupt acceptance by basic interval timer Enables interrupt acceptance by basic interval timer 42 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 7.2.4 IRQ This is an interrupt request flag that indicates the interrupt request status. When an interrupt request is generated, this flag is set to "1". When the interrupt has been accepted, the interrupt request flag is reset to "0". The interrupt request flag can be read or written by the program. Therefore, when it is set to "1", an interrupt can be generated by the software. By writing "0" to the flag, the interrupt pending status can be canceled. 3 0 2 0 1 0 0 IRQBTM Address RF : 3DH On reset 0H R/W R/W IRQBTM 0 1 Basic Interval Timer Interrupt Request Flag Interrupt request has not been made. Basic interval timer interrupt request has been made. 3 0 2 0 1 0 0 IRQ Address RF : 3EH On reset 0H R/W R/W IRQ 0 1 INT Pin Interrupt Request Flag Interrupt request has not been made. Interrupt request has been made at rising edge or falling edge of INT input. 3 0 2 0 1 0 0 IRQTM Address RF : 3FH On reset 1H Note R/W R/W IRQTM 0 1 8-Bit Timer Interrupt Request Flag Interrupt request has not been made. 8-bit timer interrupt request has been made. Note 1H is also set after releasing STOP mode. Data Sheet U12643EJ2V0DS00 43 PD17225, 17226, 17227, 17228 7.3 Interrupt Sequence If IRQxx flag is set to "1" when IPxx flag is "1", interrupt processing is started after the instruction cycle of the instruction executed when IRQxx flag was set has ended. Since the MOVT instruction, EI instruction, and the instruction which matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. If IPxx flag is "0", the interrupt processing is not performed even if IRQxx flag is set, until IPxx flag is set. If two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. The interrupt with the lower priority is kept pending until the processing of the interrupt with the higher priority is finished. 7.3.1 Operations when interrupt is accepted When an interrupt has been accepted, the CPU performs processing in the following sequence: Clears IRQxxx corresponding to INTE flag and accepted interrupt Decrements value of stack pointer by 1 (SP - 1) Saves contents of program counter to stack addressed by stack pointer Loads vector address to program counter Save contents of PSWORD to interrupt stack register One instruction cycle is required to perform the above processing. 44 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 7.3.2 Returning from interrupt processing routine To return from an interrupt processing routine, use the RETI instruction. Then the following processing is executed within an instruction cycle. Loads contents of stack addressed by stack pointer to program counter Loads contents of interrupt stack register to PSWORD Increments value of stack pointer by 1 To enable an interrupt after the processing of an interrupt has been finished, the EI instruction must be executed immediately before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, the interrupt is not accepted between the EI and RETI instructions. Data Sheet U12643EJ2V0DS00 45 PD17225, 17226, 17227, 17228 8. STANDBY FUNCTIONS PD17225 is provided with HALT and STOP modes as standby functions. By using the standby function, current consumption can be reduced. In the HALT mode, the program is not executed, but the system clock fX is not stopped. This mode is maintained, until the HALT mode release condition is satisfied. In the STOP mode, the system clock is stopped and program execution is stopped. This mode is maintained, until the STOP mode release condition is satisfied. The HALT mode is set, when the HALT instruction has been executed. The STOP mode is set, when the STOP instruction has been executed. 8.1 HALT Mode In this mode, program execution is temporarily stopped, with the main clock continuing oscillating, to reduce current consumption. Use the HALT instruction to set the HALT mode. The HALT mode releasing condition can be specified by the operand for the HALT instruction, as shown in Table 8-1. After the HALT mode has been released, the operation is performed as shown in Table 8-1 and Figure 8-2. Caution Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the HALT 8H instruction; otherwise, the HALT mode may not be set. Table 8-1. HALT Mode Releasing Conditions Operand Value 0010B (02H) Releasing Conditions When interrupt request (IRQTM) occurs for 8-bit timer <1> 1000B (08H) <2> Other Than Above When interrupt request (IRQTM, IRQWTM, or IRQ), whose interrupt enable flag (IPTM, IPBTM, or IP) is set, occurs When any of P0A0-P0A3 and P0B0-P0B3 pins goes low Setting prohibited Table 8-2. Operations After HALT Mode Release (1/2) (a) HALT 08H Interrupt Status Don't care Interrupt Enable Flag Don't care Operations after HALT Mode Release Instruction next to HALT is executed HALT Mode Released by: Low-Level Input of P0A0-P0A3, P0B0-P0B3 When Release Condition Is Satisfied by Interrupt DI Disabled Enabled Standby mode is not released Instruction next to HALT is executed Standby mode is not released Branches to interrupt vector address EI Disabled Enabled 46 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 Table 8-2. Operations After HALT Mode Release (2/2) (b) HALT 02H Interrupt Status DI Interrupt Enable Flag Disabled Enabled EI Disabled Enabled Branches to interrupt vector address Operations after HALT Mode Release Instructions are executed from the instruction next to the HALT instruction. HALT Mode Released by: 8-Bit Timer 8.2 HALT Instruction Execution Conditions The HALT instruction can be executed, only under special conditions, as shown in Table 8-3, to prevent the program from hangup. If the conditions in Table 8-3 are not satisfied, the HALT instruction is treated as an NOP instruction. Table 8-3. HALT Instruction Execution Conditions Operand Value 0010B (02H) 1000B (08H) Execution Conditions When all interrupt request flags (IRQTM) of 8-bit timer are reset <1> <2> Other Than Above When interrupt request flag is reset, corresponding to interrupt whose interrupt enable flag (IPTM, IPBTM, or IP) is set When high level is input to all P0A0-P0A3 and P0B0-P0B3 pins Setting prohibited Data Sheet U12643EJ2V0DS00 47 PD17225, 17226, 17227, 17228 8.3 STOP Mode In the STOP mode, the system clock (fX) oscillation is stopped and the program execution is stopped to minimize current consumption. To set the STOP mode, use the STOP instruction. The STOP mode releasing condition can be specified by the STOP instruction operand, as shown in Table 8-4. After the STOP mode has released, the operation is performed as follows: <1> Resets IRQTM. <2> Starts the basic interval timer and watchdog timer (does not reset). <3> Resets and starts the 8-bit timer. <4> Executes the instruction next to [STOP 8H] when the current value of the 8-bit counter coincides with the value of the modulo register (IRQTM is set). The PD17225 oscillator is stopped, when the STOP instruction has been executed (i.e., in the STOP mode). Oscillation is not resumed, until the STOP mode is released. After the STOP mode has been released, the HALT mode is set. Set the time required to release the HALT mode by using the timer with modulo function. The time that elapses, after the STOP mode has been released by occurrence of an interrupt, until an operation mode is set, is shown in the following table. 8-Bit Modulo Register Set Value (TMM) Time Required to Set Operation Mode after STOP Mode Release At 4 MHz 40H FFH 4.160 ms (64 s x 65) 16.384 ms (64 s x 256) Remark Set the 8-bit modulo timer before executing STOP instruction. Caution Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the STOP 8H instruction; otherwise, the STOP mode may not be set. Table 8-4. STOP Mode Releasing Conditions Operand Value 1000B (08H) Other Than Above Releasing Conditions When any of P0A0-P0A3 and P0B0-P0B3 pins goes low Setting prohibited 48 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 8.4 STOP Instruction Execution Conditions The STOP instruction can be executed, only under special conditions, as shown in Table 8-5, to prevent the program from hang-up. If the conditions in Table 8-5 are not satisfied, the STOP instruction is treated as an NOP instruction. Table 8-5. STOP Instruction Execution Conditions Operand Value 1000B (08H) Other Than Above Execution Conditions High level input for all P0A0-P0A3 and P0B0-P0B3 pins Setting prohibited 8.5 Releasing Standby Mode Operations for releasing the STOP and HALT modes will be as shown in Figure 8-1. Figure 8-1. Operations After Standby Mode Release (a) Releasing STOP mode by interrupt STOP instruction Stanby release signal Operation mode Oscillation Wait (time set by TMM) STOP mode Oscillation stops HALT mode Oscillation Operation mode Clock (b) Releasing HALT mode by interrupt HALT instruction Stanby release signal Operation mode HALT mode Operation mode Clock Oscillation Remark The dotted line indicates the operation to be performed when the interrupt request, releasing the standby mode, has been accepted. Data Sheet U12643EJ2V0DS00 49 PD17225, 17226, 17227, 17228 9. 9.1 RESET Reset by Reset Signal Input When a low-level signal more than 50 s is input to the RESET pin, PD17225 is reset. When the system is reset, the oscillator circuit remains in the HALT mode and then enters an operation mode, like when the STOP mode has been released. The wait time, after the reset signal has been removed, is 16.384 ms (fX = 4 MHz). On power application, input the reset signal at least once because the internal circuitry operations are not stable. When PD17225 is reset, the following initialization takes place: (1) (2) (3) (4) (5) Program counter is reset to 0. Flags in the register file are initialized to their default values (for the default values, refer to Figure 11-1 Register Files). The default value (0320H) is written to the data buffer (DBF). The hardware peripherals are initialized. The system clock (fX) stops oscillation. When the RESET pin is made high, the system clock starts oscillating, and the program execution starts from address 0 about 16 ms (at 4 MHz) later. Figure 9-1. Reset Operation by RESET Input Wait (about 16 ms at 4 MHz) RESET Operation mode or standby mode Starts from address 0H HALT mode Operation mode Oscillation stops 9.2 Reset by Watchdog Timer (Connect RESET and WDOUT pins) When the watchdog timer operates during program execution, a low level is output to the WDOUT pin, and the program counter is reset to 0. If the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H. Program so that the watchdog timer is reset at intervals of within 340 ms (at fX = 4 MHz) (set the WDTRES flag). 50 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 9.3 Reset by Stack Pointer (Connect RESET and WDOUT pins) When the value of the stack pointer reaches 6H or 7H during program execution, a low level is output to the WDOUT pin, and the program counter is reset to 0. If the nesting level of the interrupt or subroutine call exceeds 5 (stack over flow), or if the return instruction is executed without correspondence between CALL and return (RET) instructions established, then regardless of a stack level of 0 (stack underflow), the program can be restarted from address 0H. Table 9-1. Status of Each Hardware After Reset RESET Input During Standby Mode 0000H Input/output Output latch Data Memory (RAM) General-purpose data memory (Except DBF, port register) DBF System register (SYSREG) WR Input 0 Retains previous status 0320H 0 Retains previous status RESET Input During Operation 0000H Input 0 Undefined Hardware Program Counter (PC) Port 0320H 0 Undefined Control Register 8-bit Timer Counter (TMC) Modulo register (TMM) Remote Controller Carrier Generator Refer to Figure 11-1 Register Files 00H FFH 00H FFH Undefined NRZ high-level timer modulo register (NRZHTMM) Retains previous NRZ low-level timer modulo register (NRZLTMM) status 00H Basic Interval Timer/Watchdog Timer Counter 00H Data Sheet U12643EJ2V0DS00 51 PD17225, 17226, 17227, 17228 10. LOW-VOLTAGE DETECTOR CIRCUIT (CONNECT RESET AND WDOUT PINS) The low-voltage detector circuit outputs a low level from the WDOUT pin for initialization (reset) to prevent program hang-up that may take place when the batteries are replaced, if the circuit detects a low voltage. A drop in the supply voltage is detected if the status of VDD = 1.7 to 2.0 V lasts for 1 ms or longer. Note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above low-voltage condition lasts for less than 1 ms. Although the voltage at which the the reset function is effected ranges from 1.7 to 2.0 V, the program counter is prevented from hang-up even if the supply voltage drops until the reset function is effected, if the instruction execution time is from 4 to 32 s. Note that some oscillators stop oscillating before the reset function is effected. The low-voltage detector circuit can be set arbitrarily by the mask option. Caution Connect a capacitor to the RESET pin as shown below to stabilize the operation. Microcomputer RESET WDOUT Remark In this figure, the RESET pin is connected to a pull-up resistor by the mask option. 52 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 11. ASSEMBLER RESERVED WORDS 11.1 Mask Option Directives When developing the PD17225 program, mask options must be specified by using mask option directives in the program. The RESET pin for PD17225 requires a mask option to be specified. 11.1.1 OPTION and ENDOP directives That portion of the program enclosed by the OPTION and ENDOP directives is called a mask option definition block. This block is described in the following format: Description format: Symbol [Label: ] Mnemonic OPTION : : : ENDOP Operand Comment [;Comment] 11.1.2 Mask option definition directives Table 11-1 lists the directives that can be used in the mask option definition block. Here is an example of mask option definition: Description example: Symbol Mnemonic OPTION OPTRES OPTPOC ENDOP PULLUP USEPOC ; RESET pin has pull-up resistors. ; Internal low-voltage detector circuit Operand Comment Data Sheet U12643EJ2V0DS00 53 PD17225, 17226, 17227, 17228 Table 11-1. Mask Option Definition Directives Name RESET Directive OPTRES Operands 1 1st Operand Mask option of RESET PULLUP (w/pull-up resistor) OPEN (w/o pull-up resistor) POC OPTPOC 1 USEPOC (low-voltage detector circuit provided) NOUSEPOC (low-voltage detector circuit not provided) 2nd Operand 3rd Operand 4th Operand 11.2 Reserved Symbols The symbols defined by the PD17225 device file are listed in Table 11-2. The defined symbols are the following register file names, port names, and peripheral hardware names. 11.2.1 Register file The names of the symbols assigned to the register file are defined. These registers are accessed by the PEEK and POKE instructions through the window register (WR). Figure 11-1 shows the register file. 11.2.2 Registers and ports on data memory The names of the registers assigned at addresses 00H through 7FH on the data memory and the names of ports assigned to address 70H and those that follow, and system register names are defined. Figure 11-2 shows the data memory configuration. 11.2.3 Peripheral hardware The names of peripheral hardware accessed by the GET and PUT instructions are defined. Table 11-3 shows the peripheral hardware. 54 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 Table 11-2. Reserved Symbols (1/2) Symbol Name DBF3 DBF2 DBF1 DBF0 AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 P0C1 P0C2 P0C3 P0D0 P0D1 P0D2 P0D3 Attribute MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.0CH 0.0DH 0.0EH 0.0FH 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0 0.70H.0 0.70H.1 0.70H.2 0.70H.3 0.71H.0 0.71H.1 0.71H.2 0.71H.3 0.72H.0 0.72H.1 0.72H.2 0.72H.3 0.73H.0 0.73H.1 0.73H.2 0.73H.3 R/W R/W R/W R/W R/W Note R/W R/W R/W R/W Note Note Note R/W R/W R/W R/W Note R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits 15-12 of data buffer Bits 11-8 of data buffer Bits 7-4 of data buffer Bits 3-0 of data buffer Bits 15-12 of address register Bits 11-8 of address register Bits 7-4 of address register Bits 3-0 of address register Window register Bank register Index register, high Data memory row address pointer, high Memory pointer enable flag Index register, middle Data memory row address pointer, low Index register, low General register pointer, high General register pointer, low Program status word BCD flag Compare flag Carry flag Zero flag Index enable flag Bit 0 of port 0A Bit 1 of port 0A Bit 2 of port 0A Bit 3 of port 0A Bit 0 of port 0B Bit 1 of port 0B Bit 2 of port 0B Bit 3 of port 0B Bit 0 of port 0C Bit 1 of port 0C Bit 2 of port 0C Bit 3 of port 0C Bit 0 of port 0D Bit 1 of port 0D Bit 2 of port 0D Bit 3 of port 0D Note R: PD17225, 17226 R/W: PD17227, 17228 Data Sheet U12643EJ2V0DS00 55 PD17225, 17226, 17227, 17228 Table 11-2. Reserved Symbols (2/2) Symbol Name P0E0 P0E1 P0E2 P0E3 SP SYSCK WDTRES BTMCK BTMRES INT NRZBF NRZ P0EBPU0 P0EBPU1 P0EBPU2 P0EBPU3 IEG P0EBIO0 P0EBIO1 P0EBIO2 P0EBIO3 IPBTM IP IPTM TMEN TMRES TMCK1 TMCK0 IRQBTM IRQ IRQTM TMC TMM NRZLTMM NRZHTMM AR DBF IX Attribute FLG FLG FLG FLG MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG DAT DAT DAT DAT DAT DAT DAT Value 0.6FH.0 0.6FH.1 0.6FH.2 0.6FH.3 0.81H 0.82H.0 0.83H.3 0.83H.2 0.83H.1 0.8FH.0 0.91H.0 0.92H.0 0.97H.0 0.97H.1 0.97H.2 0.97H.3 0.9FH.0 0.0A7H.0 0.0A7H.1 0.0A7H.2 0.0A7H.3 0.0AFH.2 0.0AFH.1 0.0AFH.0 0.0B3H.3 0.0B3H.2 0.0B3H.1 0.0B3H.0 0.0BDH.0 0.0BEH.0 0.0BFH.0 05H 06H 03H 04H 40H 0FH 01H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W -- -- Bit 0 of port 0E Bit 1 of port 0E Bit 2 of port 0E Bit 3 of port 0E Stack pointer System clock select flag Watchdog timer reset flag Basic interval timer mode select flag Basic interval timer mode reset flag INT pin status flag NRZ buffer data flag NRZ data flag P0E0 pull-up setting flag P0E1 pull-up setting flag P0E2 pull-up setting flag P0E3 pull-up setting flag INT pin interrupt edge flag P0E0 I/O setting flag P0E1 I/O setting flag P0E2 I/O setting flag P0E3 I/O setting flag Basic interval timer interrupt enable flag INT pin interrupt enable flag Timer interrupt enable flag Timer enable flag Timer reset flag Timer clock flag Timer clock flag Basic interval timer interrupt request flag INT pin interrupt request flag Timer interrupt request flag Timer count register Timer modulo register NRZ low-level timer modulo register NRZ high-level timer modulo register Address register Fixed operand value for PUT, GET, MOVT instruction Fixed operand value for INC instruction Description 56 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 [MEMO] Data Sheet U12643EJ2V0DS00 57 PD17225, 17226, 17227, 17228 Figure 11-1. Register Files (1/2) Column Address Row Address Bit 3 0 Bit 2 Bit 1 Bit 0 Bit 3 1 Bit 2 Bit 1 Bit 0 Bit 3 2 Bit 2 Bit 1 Bit 0 Bit 3 3 Bit 2 Bit 1 Bit 0 0 Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 0 SP 1 0 0 0 0 0 0 0 0 0 0 0 0 0 NRZ 0 WDTRES 0 0 BTMCK 0 0 BTMRES 0 0 0 P0EBPU3 0 P0EBPU2 0 P0EBPU1 0 P0EBPU0 0 P0EBIO3 0 P0EBIO2 0 P0EBIO1 0 P0EBIO0 0 1 SYSCK 0 0 0 0 0 NRZBF 0 TMEN 1 TMRES 0 TMCK1 0 TMCK0 0 Note On reset Figure 11-2. Data Memory Configuration 0 0 1 Row address 2 3 4 5 6 7 1 2 3 4 5 6 Column address 7 8 9 A B C D E F DBF DBF3DBF2DBF1DBF0 P0E0-P0E3 AR3 AR2 AR1 AR0 WR BANK IXH IXM IXL RPH RPL PSW System register P0D0-P0D3 P0C0-P0C3 P0B0-P0B3 P0A0-P0A3 58 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 Figure 11-1. Register Files (2/2) Column Address Row Address Bit 3 0 Bit 2 Bit 1 Bit 0 Bit 3 1 Bit 2 Bit 1 Bit 0 Bit 3 2 Bit 2 Bit 1 Bit 0 Bit 3 3 Bit 2 Bit 1 Bit 0 8 Note 9 Note A Note B Note C Note D Note E Note F Note 0 0 0 INT 0 0 0 IEG 0 0 0 0 P 0 0 0 0 0 IPBTM 0 IP IPTM 0 0 0 0 0 0 0 0 0 IRQ 0 0 0 0 0 0 0 0 0 0 0 IRQBTM 0 0 IRQTM 1 Note On reset P: When INT pin is high level, 1 or when INT pin is low level, 0. Table 11-3. Peripheral Hardware Name TMC TMM NRZLTMM NRZHTMM AR Address 05H 06H 03H 04H 40H Valid Bit 8 8 8 8 16 Timer count register Timer modulo register Description Low-level timer modulo register for NRZ High-level timer modulo register for NRZ Address register Data Sheet U12643EJ2V0DS00 59 PD17225, 17226, 17227, 17228 12. INSTRUCTION SET 12.1 Instruction Set Outline b15 b14-b11 BIN. 0000 0001 0010 0011 0100 0101 0110 HEX. 0 1 2 3 4 5 6 ADD SUB ADDC SUBC AND XOR OR INC INC MOVT BR CALL RET RETSK EI DI RETI PUSH POP GET PUT PEEK POKE RORC STOP HALT NOP LD SKE MOV SKNE BR BR BR BR r, m r, m r, m r, m r, m r, m r, m AR IX DBF, @AR @AR @AR ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 0 1 0111 7 AR AR DBF, p p, DBF WR, rf rf, WR r s h 1000 1001 1010 1011 1100 1101 1110 1111 8 9 A B C D E F r, m m, #n4 @r, m m, #n4 addr (Page 0) addr (Page 1) addr (Page 2) addr (Page 3) ST SKGE MOV SKLT CALL MOV SKT SKF m, r m, #n4 m, @r m, #n4 addr m, #n4 m, #n m, #n 60 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 12.2 AR ASR addr BANK CMP CY DBF h INTEF INTR INTSK IX MP MPE m mR mC n n4 PAGE PC p pH pL r rf rfR rfC SP s WR (x) Legend : Address register : Address stack register specified by stack pointer : Program memory address (low-order 11 bits) : Bank register : Compare register : Carry flag : Data buffer : Halt releasing condition : Interrupt enable flag : Register automatically saved to stack in case of interrupt : Interrupt stack register : Index register : Data memory row address pointer : Memory pointer enable flag : Data memory address specified by mR, mC : Data memory row address (high) : Data memory column address (low) : Bit position (4 bits) : Immediate data (4 bits) : Page (bit 11 and 12 of program counter) : Program counter : Peripheral address : Peripheral address (high-order 3 bits) : Peripheral address (low-order 4 bits) : General register column address : Register file address : Register file row address (high-order 3 bits) : Register file column address (low-order 4 bits) : Stack pointer : Stop releasing condition : Window register : Contents addressed by x Data Sheet U12643EJ2V0DS00 61 PD17225, 17226, 17227, 17228 12.3 List of Instruction Sets Instruction Code OP Code ADD r, m m, #n4 Addition ADDC r, m m, #n4 INC AR IX SUB Subtraction SUBC r, m m, #n4 r, m m, #n4 OR r, m m, #n4 Logical AND r, m m, #n4 XOR SKT SKF SKE Compare SKNE SKGE SKLT r, m m, #n4 Judge m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY AR AR + 1 IX IX + 1 (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 11110 11111 01001 01011 11001 11011 mR mR mR mR 000 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR Operand mC mC mC mC 1001 1000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 Group Mnemonic Operand Operation (m) (m) (m) n4 (r) (r) (m) (m) (m) n4 (r) (r) (r) (r) (m) (m) (m) n4 n = n, then skip CMP 0, if (m) n = 0, then skip CMP 0, if (m) (m) - n4, skip if zero (m) - n4, skip if not zero (m) - n4, skip if not borrow (m) - n4, skip if borrow Rotate RORC r CY (r)b3 (r)b2 (r)b1 (r)b0 00111 000 0111 r LD ST r, m m, r @r, m (r) (m) (m) (r) if MPE = 1 : (MP, (r)) (m) if MPE = 0 : (BANK, mR, (r)) (m) if MPE = 1 : (m) (MP, (r)) if MPE = 0 : (m) (BANK, mR, (r)) (m) n4 SP SP - 1, ASR PC, PC AR DBF (PC), PC ASR, SP SP + 1 01000 11000 01010 mR mR mR mC mC mC r r r Transfer MOV m, @r 11010 mR mC r m, #n4 MOVT DBF, @AR 11101 00111 mR 000 mC 0001 n4 0000 62 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 Instruction Code OP Code PUSH POP Transfer PEEK POKE GET PUT Branch BR AR AR WR, rf rf, WR DBF, p p, DBF addr @AR addr CALL @AR Subroutine RET RETSK RETI Interrupt EI DI STOP Other HALT NOP s h SP SP - 1, ASR AR AR ASR, SP SP + 1 WR (rf) (rf) WR (DBF) (p) (p) (DBF) Note PC AR SP SP - 1, ASR PC, PC10-0 addr, PAGE 0 SP SP - 1, ASR PC, PC AR PC ASR, SP SP + 1 PC ASR, SP SP + 1 and skip PC ASR, INTR INTSK, SP SP + 1 INTEF 1 INTEF 0 STOP HALT No operation 00111 00111 00111 00111 00111 00111 01100 00111 11100 000 000 000 rfR rfR pH pH Operand 1101 1100 0011 0010 1011 1010 addr 0100 addr 0000 0000 0000 rfC rfC pL pL Group Mnemonic Operand Operation 00111 000 0101 0000 00111 00111 00111 00111 00111 00111 00111 00111 000 001 100 000 001 010 011 100 1110 1110 1110 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 s h 0000 Note The operation and OP code of "BR addr" of the PD17225, 17226, 17227, and 17228 are as follows, respectively. (a) PD17225 Operand addr PC10-0 addr Operation OP Code 01100 (b) PD17226 Operand addr Operation PC10-0 addr, PAGE 0 PC10-0 addr, PAGE 1 OP Code 01100 01101 (c) PD17227 Operand addr Operation PC10-0 addr, PAGE 0 PC10-0 addr, PAGE 1 PC10-0 addr, PAGE 2 OP Code 01100 01101 01110 Data Sheet U12643EJ2V0DS00 63 PD17225, 17226, 17227, 17228 (d) PD17228 Operand addr Operation PC10-0 addr, PAGE 0 PC10-0 addr, PAGE 1 PC10-0 addr, PAGE 2 PC10-0 addr, PAGE 3 OP Code 01100 01101 01110 01111 12.4 Assembler (RA17K) Built-In Macro Instruction Legend flag n : FLG type symbol n < : Bit number > : Contents in < Mnemonic Built-in macro SKTn SKFn SETn CLRn NOTn INITFLG > can be omitted Operand flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n BANKn Expantion instruction BRX CALLX INITFLGX Note PD17227, 17228: n = 0, 1 64 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 13. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Item Supply Voltage Input Voltage Output Voltage High-Level Output Current Note Symbol VDD VI VO IOH REM pin Conditions Ratings -0.3 to +3.8 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Peak value rms value -36.0 -24.0 -7.5 -5.0 -22.5 -15.0 7.5 5.0 22.5 15.0 30.0 20.0 -40 to +85 -65 to +150 Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA C C mW 1 pin (P0E pin) Peak value rms value Total of P0E pins Peak value rms value Low-Level Output Current Note IOL 1 pin (P0C, P0D, P0E, REM or WDOUT pin) Total of P0C, P0D, WDOUT pins Total of P0E pins Peak value rms value Peak value rms value Peak value rms value Operating Temperature Storage Temperature Power Dissipation TA Tstg Pd TA = 85 C 180 Note Calculate rms value by this expression: [rms value] = [Peak value] x Duty Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. Data Sheet U12643EJ2V0DS00 65 PD17225, 17226, 17227, 17228 Recommended Operating Ranges (TA = -40 to +85C, VDD = 2.0 to 3.6 V) Item Supply Voltage Symbol VDD1 fX = 1 MHz Conditions High-speed mode (Instruction execution time: 16 s) Ordinary mode (Instruction execution time: 4 s) High-speed mode (Instruction execution time: 4 s) High-speed mode (Instruction execution time: 2 s) 2.2 3.6 V MIN. 2.0 TYP. MAX. 3.6 Unit V VDD2 fX = 4 MHz VDD3 fX = 8 MHz VDD4 Oscillation Frequency Operating Temperature Low-Voltage Detector Circuit (Mask Option) Note fX TA TCY 1.0 -40 4 4.0 +25 8.0 +85 32 MHz C s Note Reset if the status of VDD = 1.7 to 2.0 V lasts for 1 ms or longer. Program hang-up does not occur even if the voltage drops, until the reset function is effected (when the RESET pin and WDOUT pin are connected). Some oscillators stop oscillating before the reset function is effected. fX vs VDD (MHZ) 10 9 8 7 6 5 System clock: fX (MHz) (Ordinary mode) 4 3 Operation guaranteed area 2 1 0.4 0 2 2.2 3 3.6 4 Supply voltage: VDD (V) Remark The region indicated by the broken line in the above figure is the guaranteed operating range in the highspeed mode. 66 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V) Resonator Ceramic resonator Recommended Constants Item Oscillation frequency Note 1 (fX) Conditions MIN. 1.0 TYP. 4.0 MAX. 8.0 Unit MHz XIN XOUT Oscillation stabilization timeNote 2 After VDD reached MIN. in oscillation voltage range 4 ms Notes 1. The oscillation frequency only indicates the oscillator characteristics. 2. The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode release. Caution To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: * Keep wiring length as short as possible. * Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of lines through which a large current flows. * Always keep the oscillator circuit capacitor ground at the same potential as GND. Do not ground the capacitor to a ground pattern, through which a large current flows. * Do not extract signals from the oscillator circuit. External circuit example XIN XOUT R1 C1 C2 Data Sheet U12643EJ2V0DS00 67 PD17225, 17226, 17227, 17228 Main System Clock: Ceramic Resonator (TA = -40 to +85 C) Recommended Circuit Constants C1 (pF) Murata Mfg. Co., Ltd. CSA2.00MG CSA3.00MG CSA4.00MG CSA6.00MG CSA8.00MTZ TDK Corp. CCR1000K2 CCR4.0MC3 CCR6.0MC3 CCR8.0MC5 FCR4.0MC5 FCR6.0MC5 Matsushita Electronic Components Co., Ltd. EF0EC2004A4 EF0EC3004A4 EF0EC4004A4 EF0EC6004A4 EF0EC8004A4 Toko Ceramic Co., Ltd. CRHF2.50 CRHF4.00 CRHF6.00 30 30 30 30 30 100 -- -- -- -- -- -- -- -- -- -- 30 30 30 C2 (pF) 30 30 30 30 30 100 -- -- -- -- -- -- -- -- -- -- 30 30 30 Oscillation Voltage Range MIN. (V) 2.0 2.0 2.0 2.0 2.2 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.2 2.2 2.2 MAX. (V) 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Manufacturer Part Number Remark Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 68 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V) Item High-Level Input Voltage Symbol VIH1 VIH2 Low-Level Input Voltage VIL1 VIL2 VIL3 High-Level Input Leakage Current Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current Internal Pull-Up Resistor ILIH P0A, P0B P0E, RESET, INT P0A, P0B P0E RESET, INT pin P0A, P0B, P0E, RESET, INT INT P0E, RESET P0C, P0D, P0E, WDOUT P0E, WDOUT VI = VDD Conditions MIN. 0.7VDD 0.8VDD 0 0 0 TYP. MAX. VDD VDD 0.3VDD 0.35VDD 0.2VDD 3 Unit V V V V V A A A A A k k mA V V ILIL1 ILIL2 ILOH VI = 0 V VI = 0 V w/o pull-up resistor VO = VDD -3 -3 3 ILOL VO = 0 V w/o pull-up resistor -3 RU1 RU2 P0E, RESET P0A, P0B REM P0E, REM P0C, P0D, REM, WDOUT P0E WDOUT = low level VOH = 1.0 V, VDD = 3 V IOH = -0.5 mA IOL = 0.5 mA 25 100 -6 VDD-0.3 50 200 -13 100 400 -24 VDD 0.3 High-Level Output Current High-Level Output Voltage Low-Level Output Voltage IOH1 VOH VOL1 VOL2 Low-Voltage Detector Circuit (Mask Option) Data Retention Voltage Supply Current VDT IOL = 1.5 mA VDT = VDD 1.7 1.85 0.3 2.0 V V VDDDR IDD1 RESET = low level or STOP mode Operating mode (high-speed) VDD = 3 V 10 % fX = 1 MHz fX = 4 MHz fX = 8 MHz 1.3 0.6 0.75 0.9 0.475 0.6 0.8 0.4 0.45 0.5 2.0 TA = 25 C 2.0 1.2 1.3 1.8 0.95 1.1 1.6 0.8 0.85 1.0 20.0 5.0 V mA mA mA mA mA mA mA mA mA IDD2 Operating mode (low-speed) VDD = 3 V 10 % fX = 1 MHz fX = 4 MHz fX = 8 MHz IDD3 HALT mode VDD = 3 V 10 % fX = 1 MHz fX = 4 MHz fX = 8 MHz IDD4 STOP mode VDD = 3 V 10 % built-in POC A A Data Sheet U12643EJ2V0DS00 69 PD17225, 17226, 17227, 17228 AC Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V) Item CPU Clock Cycle Time (Instruction Execution Time) INT High/Low Level Width RESET Low Level Width Note Symbol tCY1 tCY2 tINTH, tINTL tRSL VDD = 2.2 to 3.6 V Conditions MIN. 3.8 1.9 20 10 TYP. MAX. 33 33 Unit s s s s Note The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator connected and SYSCK (RF: address 02H) of the register file. The figure on the right shows the CPU clock cycle time CLOCK GENERATOR CIRCUIT). CPU clock cycle time tcY ( s) 40 33 tCY vs VDD tCY vs. supply voltage VDD characteristics (refer to 4. 10 9 8 7 6 5 4 3 3.8 Operation guaranteed area 2 1.9 1 0 1 2.2 2 3 3.6 4 Supply voltage VDD (V) 70 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 14. APPLICATION CIRCUIT EXAMPLE P0D2 P0D3 INT P0E0 P0E1 P0E2 P0E3 REM 3V VDD XOUT 4 MHz XIN GND RESET WDOUT 1 2 3 4 5 28 27 26 25 24 P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0 PD17225CT/GT- xxx PD17226CT/GT- xxx PD17227CT/GT- xxx PD17228CT/GT- xxx 6 7 8 9 10 11 12 13 14 23 22 21 20 19 18 17 16 15 Remark The RESET pin can be connected to a pull-up resistor by the mask option. Data Sheet U12643EJ2V0DS00 71 PD17225, 17226, 17227, 17228 15. PACKAGE DRAWINGS 28 PIN PLASTIC SHRINK DIP (400 mil) 28 15 1 A 14 K I L J G H F D N M C B M R NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 28.46 MAX. 2.67 MAX. 1.778 (T.P.) 0.500.10 0.85 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 10.16 (T.P.) 8.6 0.25 +0.10 -0.05 0.17 0~15 INCHES 1.121 MAX. 0.106 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.033 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.400 (T.P.) 0.339 0.010 +0.004 -0.003 0.007 0~15 S28C-70-400B-1 72 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 28-PIN PLASTIC SOP (375 mil) 28 15 detail of lead end P 1 A H G I J 14 F S C D E M M B K L N S NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P MILLIMETERS 17.90.17 0.78 MAX. 1.27 (T.P.) 0.42 +0.08 -0.07 0.10.1 2.60.2 2.50 10.30.3 7.20.2 1.60.2 0.17 +0.08 -0.07 0.80.2 0.12 0.15 +7 3 -3 P28GM-50-375B-4 Data Sheet U12643EJ2V0DS00 73 PD17225, 17226, 17227, 17228 30 PIN PLASTIC SSOP (300 mil) 30 16 detail of lead end F G T P 1 A 15 E L U H I J S C D NOTE N M M S B K ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 9.850.15 0.45 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S30MC-65-5A4-1 Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 74 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 16. RECOMMENDED SOLDERING CONDITIONS For the PD17225 soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For other soldering methods, please consult with NEC personnel. Table 16-1. Soldering Conditions of Surface Mount Type (1) PD17225GT-xxx: PD17226GT-xxx: PD17227GT-xxx: PD17228GT-xxx: Soldering Method Infrated Reflow VPS Wave Soldering Partial Heating 28-pin 28-pin 28-pin 28-pin plastic plastic plastic plastic SOP SOP SOP SOP (375 (375 (375 (375 mil) mil) mil) mil) Symbol IR35-00-2 VP15-00-2 WS66-00-1 -- Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 2 max. Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), Number of times: 2 max. Solder bath temperature: 260 C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120 C max. (package surface temperature) Pin temperature: 300 C max., Time: 3 seconds max. (per side of device) Caution Do not use two or more soldering methods in combination (except the partial heating method). (2) PD17225MC-xxx-5A4: PD17226MC-xxx-5A4: PD17227MC-xxx-5A4: PD17228MC-xxx-5A4: Soldering Method Infrated Reflow VPS Wave Soldering Partial Heating 30-pin 30-pin 30-pin 30-pin plastic plastic plastic plastic shrink shrink shrink shrink SOP SOP SOP SOP (300 (300 (300 (300 mil) mil) mil) mil) Symbol IR35-00-3 VP15-00-3 WS66-00-1 -- Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 3 max. Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), Number of times: 3 max. Solder bath temperature: 260 C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120 C max. (package surface temperature) Pin temperature: 300 C max., Time: 3 seconds max. (per side of device) Caution Do not use two or more soldering methods in combination (except the partial heating method). Table 16-2. Soldering Conditions of Through-Hole Type PD17225CT-xxx: PD17226CT-xxx: PD17227CT-xxx: PD17228CT-xxx: Soldering Method Wave Soldering (Only for pins) Partial Heating 28-pin 28-pin 28-pin 28-pin plastic plastic plastic plastic shrink shrink shrink shrink DIP DIP DIP DIP (400 (400 (400 (400 mil) mil) mil) mil) Soldering Conditions Solder bath temperature: 260 C max., Time: 10 seconds max. Pin temperature: 300 C max., Time: 3 seconds max. (per pin) Caution The wave solding must be performed at the lead part only. Note that the solder must not be directly contacted to the package body. Data Sheet U12643EJ2V0DS00 75 PD17225, 17226, 17227, 17228 APPENDIX A. DIFFERENCES AMONG PD17225, 17226, 17227, 17228 AND PD17P218 PD17P218 is equipped with PROM to which data can be written by the user instead of the internal mask ROM (program memory) of the PD17228. Table A-1 shows the differences between the PD17225, 17226, 17227, 17228 and PD17P218. The differences among these five models are the program memory and mask option, and their CPU functions and internal hardware are identical. Therefore, the PD17P218 can be used to evaluate the program developed for the PD17225, 17226, 17227, and 17228 system. Note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the PD17P218 are different from those of the PD17225, 17226, 17227, and 17228. Table A-1. Differences among PD17225, 17226, 17227, 17228 and PD17P218 Product Name Item Program Memory One-time PROM 16 K bytes (8192 x 16) (0000H-1FFFH) Data Memory Pull-Up Resistor of RESET Pin Low-Voltage Detector Circuit Note PD17P218 PD17225 PD17226 PD17227 PD17228 Mask ROM 4 K bytes (2048 x 16) (0000H-07FFH) 8 K bytes (4096 x 16) (0000H-0FFFH) 12 K bytes (6144 x 16) (0000H-17FFH) 16 K bytes (8192 x 16) (0000H-1FFFH) 223 x 4 bits Provided Provided Provided 111 x 4 bits Any (mask option) Any (mask option) Not provided 223 x 4 bits VPP Pin, Operation Mode Select Pin Handling of WDOUT Pin When Not Used Connect to GND Instruction Execution Time (TCY) 2 s (VDD = 3.5 to 5.5 V) 4 s (VDD = 2.2 to 5.5 V) 8 s (VDD = 2.0 to 5.5 V) Operation When P0C, P0D Are Standby Supply Voltage Package VDD = 2.0 to 5.5 V Connect to VDD via resistor 2 s (VDD = 2.2 to 3.6 V) 4 s (VDD = 2.0 to 3.6 V) Retain output level immediately before standby mode VDD = 2.0 to 3.6 V 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) 30-pin plastic shrink SOP (300 mil) Note Although the circuit configuration is identical, its electrical characteristics differ depending on the product. 76 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 [MEMO] Data Sheet U12643EJ2V0DS00 77 PD17225, 17226, 17227, 17228 APPENDIX B. FUNCTIONAL COMPARISON OF PD17225 SUBSERIES RELATED PRODUCTS Product Name PD17201A PD17207 PD17202A PD17215 Item ROM Capacity (Bit) RAM Capacity (Bit) LCD Controller/Driver 3072 x 16 4096 x 16 2048 x 16 112 x 4 96 segments max. 4096 x 16 111 x 4 Not provided 6144 x 16 8192 x 16 PD17216 PD17217 PD17218 336 x 4 136 segments max. 223 x 4 Infrared Remote Controller Carrier Generator (REM) I/O Ports External Interrupt (INT) LED output is high-active LED output is low-active 19 lines 1 line (rising-edge detection) 4 channels (8-bit A/D) 2 channels Provided (without LED output) 16 lines 20 lines 1 line (rising-edge, falling-edge detection) Analog Input Timer Not provided 2 channels 8-bit timer Watch timer 8-bit timer Basic interval timer Watchdog Timer Low-Voltage Detector Circuit Serial Interface Stack Instruction Execution Time Main System Clock Note Provided (WDOUT output) Not provided 1 channel Provided (WDOUT output) Not provided 5 levels (3 levels for multiplexed interrupt) 4 s (4 MHz: with ceramic or crystal resonator, VDD = 2.2 to 5.5 V) * 2 s (8 MHz ceramic resonator: in high-speed mode, VDD = 3.5 to 5.5 V) * 4 s (4 MHz ceramic resonator: in high-speed mode, VDD = 2.2 to 5.5 V) * 8 s (2 MHz ceramic resonator: in high-speed mode, VDD = 2.0 to 5.5 V) Not provided Subsystem Clock Supply Voltage (With Subsystem Clock) Standby Function Package 488 s (32.768 kHz: with crystal resonator, VDD = 2.0 to 5.5 V) VDD = 2.2 to 5.5 V (VDD = 2.0 to 5.5 V) VDD = 2.0 to 5.5 V STOP, HALT 80-pin plastic QFP 64-pin plastic QFP 28-pin plastic SOP 28-pin plastic shrink DIP One-Time PROM Products PD17P207 PD17P202A PD17P218 Note Note that although all the products have the same circuit construction, the electrical specifications differ dependant on each product. 78 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 PD17225 PD17226 2048 x 16 4096 x 16 PD17227 6144 x 16 PD17228 8192 x 16 111 x 4 Not provided 223 x 4 Provided (without LED output) 20 pins 1 pin (rising edge, falling edge detection) Not provided 2 channels 8-bit timer Basic interval timer Provided (WDOUT output) Provided (WDOUT output) Not provided 5 levels (3 nesting levels) * 2 s (8-MHz ceramic resonator: in high-speed mode, VDD = 2.2 to 3.6 V) * 4 s (4-MHz ceramic resonator: in high-speed mode, VDD = 2.0 to 3.6 V) Not provided VDD = 2.0 to 3.6 V STOP, HALT 28-pin plastic SOP 28-pin plastic shrink DIP 30-pin plastic shrink SOP PD17P218 Data Sheet U12643EJ2V0DS00 79 PD17225, 17226, 17227, 17228 APPENDIX C. DEVELOPMENT TOOLS To develop the programs for the PD17225 subseries, the following development tools are available: Hardware Name In-Circuit Emulator IE-17K, IE-17K-ETNote 1 Remarks IE-17K and IE-17K-ET are the in-circuit emulators used in common with the 17K series microcontroller. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM compatible machines as the host machine with RS-232C. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOST TM. This is an SE board for PD17225 subseries. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. EP-17K28CT is an emulation probe for 17K series 28-pin shrink DIP (400mil). SE Board (SE-17225) Emulation Probe (EP-17K28CT) Emulation Probe (EP-17K28GT) Emulation Probe (EP-17K30GS) Conversion Adapter (EV-9500GT-28 Note 2 EP-17K28GT is an emulation probe for 17K series 28-pin SOP (375 mil). When used with EV-9500GT-28Note 2, it connects an SE board to the target system. EP-17K30GS is an emulation probe for 17K series 30-pin shrink SOP (300 mil) (under development). EV-9500GT-28 is a conversion adapter for 28-pin SOP (375 mil) and is used to connect ) EP-17K28GT to the target system. AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers corresponding to PD17P218. By connecting program adapter AF-9808J or AF-9808H to this PROM programmer, PD17P218 can be programmed. AF-9808J and AF-9808H are adapters that is used to program PD17P218CT and PD17P218GT respectively, and is used in combination with AF-9703, AF-9704, AF-9705, or AF-9706. PROM Programmer (AF-9703Note 3, AF-9704Note 3, AF-9705Note 3, AF-9706Note 3) Program Adapter (AF-9808JNote 3, AF-9808HNote 3) Notes 1. Low-cost model: External power supply type 2. Two EV-9500GT-28s are supplied with the EP-17K28GT. Five EV-9500GT-28s are optionally available as a set. 3. These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd. (Tel: 03-37331163). 80 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 Software Name 17K Assembler (RA17K) Outline The RA17K is an assembler common to the 17K series products. When developing the program of devices, RA17K is used in combination with a device file (AS17225). The emlC-17K is a C-like compiler common to the 17K series. Used in combination with the RA17K. Host Machine PC-9800 series IBM PC/AT compatible machine OS Japanese Windows TM Supply 3.5" 2HD Order Code SAA13RA17K SAB13RA17K SBB13RA17K Japanese Windows 3.5" 2HC English Windows 17K Series C-like Compiler TM (emlC-17K ) PC-9800 series IBM PC/AT compatible machine Japanese Windows 3.5" 2HD SAA13CC17K SAB13CC17K SBB13CC17K Japanese Windows 3.5" 2HC English Windows Device File (AS17225) The AS17225 is a device file for PD17225, 17226, 17227, and 17228 respectively, and are used in combination with an assembler for the 17K series (RA17K). PC-9800 series IBM PC/AT compatible machine Japanese Windows 3.5" 2HD SAA13AS17225 SAB13AS17225 SBB13AS17225 Japanese Windows 3.5" 2HC English Windows Support Software (SIMPLEHOST) SIMPLEHOST is a software package that enables man-machine interface on the Windows when a program is developed by using an in-circuit emulator and a personal computer. PC-9800 series IBM PC/AT compatible machine Japanese Windows 3.5" 2HD SAA13ID17K SAB13ID17K SBB13ID17K Japanese Windows 3.5" 2HC English Windows Data Sheet U12643EJ2V0DS00 81 PD17225, 17226, 17227, 17228 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 82 Data Sheet U12643EJ2V0DS00 PD17225, 17226, 17227, 17228 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U12643EJ2V0DS00 83 PD17225, 17226, 17227, 17228 emlC-17K and SIMPLEHOST are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8 |
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